1. Field of the Invention
The present invention relates to a semiconductor device including a circuit for producing an internal clock signal phase-locked with an external clock signal, and more particularly to a semiconductor device producing a plurality of internal clock signals at least having different phases.
2. Description of the Background Art
In clock synchronous type devices, data transfer and processing is performed in synchronization with a clock signal. In such clock synchronous type devices, an internal clock signal synchronized with an external system clock, for example, is generated and a variety of internal operations are performed in synchronization with the internal clock signal. In a field of communication, for example, an internal clock signal is generated by reproducing a clock signal from received data, and the received data is processed in synchronization with this internal clock signal, or at the time of data transmission, data is sent in synchronization with the clock signal.
Furthermore, in clock synchronous type semiconductor memory devices, data, control signals and address signals externally applied are taken-in in synchronization with a clock signal and data is transferred in synchronization with the clock signal. For this clock synchronous operation, an internal clock signal synchronized with an external clock signal is internally generated, and signal/data taking-in and output transfer are performed in synchronization with this internal clock signal.
A PLL (Phase Locked Loop) circuit is generally used as a circuit for generating an internal clock signal phase-locked with a reference clock signal such as an external (system) clock signal. In the PLL circuit, a reference clock signal and an internal clock signal are compared in phase, and a signal in accordance with the phase difference is generated using a charger pump. An output signal of this charger pump is usually generated by a charged voltage of a capacitance element, and an oscillation frequency of an oscillation circuit is adjusted in accordance with the output signal of this charger pump. When the reference signal and the internal clock signal are matched in phase, the output signal of the charger pump is kept constant and the oscillation circuit oscillates at a constant oscillation frequency. The output signal of this oscillation circuit is utilized as the internal clock signal.
The oscillation circuit includes a current controlled oscillation circuit in which an oscillation frequency is adjusted by a control current and a voltage controlled oscillation circuit in which an oscillation frequency is adjusted by a control voltage.
In a PLL circuit, it is necessary to generate an internal clock signal accurately phase-locked with a reference clock signal without the effect of jitter and the like. A configuration of changing bandwidths and transient response characteristics of PLL circuit depending on a variety of usage, is disclosed in a prior art document 1 (Japanese Patent Laying-Open No. 63-87019). In the configuration in the prior art document 1, two phase-locked circuits receiving the same input signal are used, and an oscillation control signal output by one phase locked circuit is transmitted to the other phase locked circuit. In the other phase locked circuit, this oscillation control signal is mixed to adjust the oscillation frequency, thereby generating an internal clock signal.
In the prior art document 1, a phase comparison result of a first phase locked circuit is applied to a second phase locked circuit through an attenuator and an inverter. In the second phase locked circuit, an output signal from a second phase comparator is added to a signal transferred through the attenuator and the inverter from a first phase comparator to generate an oscillation control signal. By changing an attenuation ratio depending on received signal conditions, the order of closed loop transfer characteristic of this phase locked circuit is adjusted. More specifically, when the attenuation ratio is zero, the closed loop transfer characteristic is set to a second-order characteristic, and when the attenuation ratio is unity, the closed loop transfer function of this phase locked circuit is set to a function of a fourth-order characteristic. This attenuation ratio is set to zero for improving the transient response characteristics in a broad bandwidth, and to unity for enhancing the effect of suppressing jitter in a narrow bandwidth.
In the configuration of the prior art document 1 as described above, a clock signal is applied in common to the first and second phase locked circuits. A phase comparison result in the first phase locked circuit is applied to the second phase locked circuit through an attenuator and an inverter, a result of phase comparison between the a basic clock signal and an output clock signal in the second phase locked circuit is added to a phase comparison result supplied from the first phase locked circuit, and a result of the addition is applied to a voltage controlled oscillation circuit through a loop filter. In accordance with the addition result supplied through this loop filter, an oscillation frequency of the voltage controlled oscillation circuit in the second phase locked circuit is adjusted, whereby an output clock signal is generated.
Therefore, in the configuration of the prior art document 1, two phase-locked circuits are used for generating one kind of internal clock signal from a basic clock signal. When only one kind of internal clock signal is used in a semiconductor device, the configuration of the prior art document 1 can be used, in spite of its area penalty.
In some semiconductor devices, however, a plurality of internal clock signals having phases and/or frequencies slightly different from a basic clock signal may be required. Such cases includes, for example, a case where an internal clock signal is produced in synchronization with a signal input to a semiconductor device and an input signal is processed in accordance with this internal clock signal while an output signal is sent in accordance with a basic clock signal. The input signal (data) is generated based on a sending clock signal generated from the basic clock signal at the sending-side. Therefore, because of the transfer characteristics in this signal/clock transmission path, the input signal has its phase/frequency shifted from the basic clock signal. In particular, when in a semiconductor device an internal basic clock signal is generated by a clock buffer circuit and each data/signal taking-in is performed by an input buffer, internal clock propagation delay must be considered. Therefore, in order to accurately process the input signal, a clock signal synchronized with the input signal has to be generated.
Furthermore, when externally transferred data/signals are transferred at a different speed by a different device due to operation characteristics of external devices and the like, it is required to generate an internal signal synchronized with these data/signals for taking in data/signals. In this case, although the phases/frequencies of the signals/data are close to each other, an internal clock signal from one PLL circuit cannot be used to accurately take in these signals/data. In particular, when a transfer is performed in synchronization with a fast clock signal, an effect of a small phase/frequency shift is increased to make it difficult to take in signals/data accurately.
As a method of taking in such signals/data, it can be contemplated to provide phase locked circuits for synchronization object signals to generate internal clock signals synchronized with the respective synchronization object signals.
When such a plurality of phase locked circuits are provided, a plurality of phase locked circuits perform individual phase synchronization operations independently. Therefore, when an oscillation frequency of one phase locked circuit is stable, an oscillation frequency of another phase locked circuit is not always stable, resulting in that a long time is required to stabilize the oscillation frequency in each of the phase locked circuits.
Furthermore, where the frequencies of processed signals are different in these plurality of phase locked circuits and where separate phase locked circuits are provided, respective frequency adjusting circuits have to be provided in order to attain the identical operation characteristics among the separate phase locked circuits, resulting in an increased area occupied by the circuitry generating internal clock signals.